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1/51 september 2003 m58lw032d 32 mbit (4mb x8, 2mb x16, uniform block) 3v supply flash memory features summary n wide x8 or x16 data bus for high bandwidth n supply voltage Cv dd = v ddq = 2.7 to 3.6v for program, erase and read operations n access time C random read 90ns,110ns C page mode read 90ns/25ns, 110ns/25ns n programming time C 16 word write buffer C12 m s word effective programming time n 32 uniform 64 kword/128kbyte memory blocks n enhanced security C block protection/ unprotection Cv pen signal for program erase enable C 128 bit protection register with 64 bit unique code in otp area n program and erase su spend n 128 bit protection register n common flash interface n 100, 000 program/er ase cycles per block n electronic signature C manufacturer code: 0020h C device code m58lw032d: 0016h figure 1. packages tsop56 (n) 14 x 20 mm tbga64 (za) 10 x 13 mm tbga
m58lw032d 2/51 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. tsop56 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. tbga64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address input (a0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address inputs (a1-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data inputs/outputs (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 chip enables (e0, e1, e2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 byte/word organization select (byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 status/(ready/busy) (sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 program/erase enable (v pen ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. device enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 read query command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 word/byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 write to buffer and program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/51 m58lw032d program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block protect command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 blocks unprotect command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 configure sts command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. protection register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. word-wide read protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. byte-wide read protection register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . 20 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program/erase controller status (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 erase suspend status (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 erase status (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program status (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 vpen status (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 program suspend status (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block protection status (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 reserved (sr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. ac measurement input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 13. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. bus read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 11. write ac waveform, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12. write ac waveforms, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13. reset, power-down and power-up ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 19. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
m58lw032d 4/51 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . 32 table 20. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data 32 figure 15. tbga64 - 10x13mm, 8 x 8 ball array 1mm pitch, package outline . . . . . . . . . . . . . . . 33 table 21. tbga64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, package mechanical data. . . . . . . 33 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 appendix a. block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 23. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 appendix b. common flash interface - cfi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 24. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 25. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 26. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 27. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 28. block status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 29. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 appendix c. flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16. write to buffer and program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 40 figure 17. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 41 figure 18. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 19. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. block protect flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. block unprotect flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 46 figure 23. command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . 47 figure 24. command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . 48 figure 25. command interface and program erase controller flowchart (c). . . . . . . . . . . . . . . . 49 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5/51 m58lw032d summary description the m58lw032d is a 32 mbit (4mb x 8 or 2mb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be per- formed using a single low voltage (2.7v to 3.6v) core supply. the memory is divided into 32 blocks of 1mbit that can be erased independently so it is possible to preserve valid data while old data is erased. pro- gram and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. the write buffer allows the microprocessor to pro- gram from 1 to 16 words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. a word program command is available to program a single word. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. the m58lw032d has several security features to increase data protection. n block protection, where each block can be individually protected against program or erase operations. all blocks are protected during power-up. the protection of the blocks is non- volatile; after power-up the protection status of each block is restored to the state when power was last removed. n program erase enable input v pen , program or erase operations are not possible when the program erase enable input v pen is low. n 128 bit protection register, divided into two 64 bit segments: the first contains a unique device number written by st, the second is user programmable. the user programmable segment can be protected. the reset/power-down pin is used to apply a hardware reset to the enabled memory and to set the device in power-down mode. the device features an auto low power mode. if the bus becomes inactive during read operations, the device automatically enters auto low power mode. in this mode the power consumption is re- duced to the auto low power supply current. the sts signal is an open drain output that can be used to identify the program/erase controller sta- tus. it can be configured in two modes: ready/ busy mode where a static signal indicates the sta- tus of the p/e.c, and status mode where a pulsing signal indicates the end of a program or block erase operation. in status mode it can be used as a system interrupt signal, useful for saving cpu time. the memory is available in tsop56 (14 x 20 mm) and tbga64 (10x13mm , 1mm pitch) packages.
m58lw032d 6/51 figure 2. logic diagram table 1. signal names ai06234b 22 a0-a21 w dq0-dq15 m58lw032d e0 v ss 16 g rp e1 e2 v pen v ssq sts byte v dd v ddq a0 address input (used in x8 mode only) a1-a21 address inputs byte byte/word organization select dq0-dq15 data inputs/outputs e0 chip enable e1 chip enable e2 chip enable g output enable rp reset/power-down sts status/(ready/busy) v pen program/erase enable w write enable v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground nc not connected internally du do not use
7/51 m58lw032d figure 3. tsop56 connections dq3 dq9 dq2 dq0 dq6 a16 a17 a18 dq14 dq12 dq10 sts v ddq dq4 dq7 ai06235 m58lw032d 14 1 15 28 29 42 43 56 dq8 v dd dq1 dq11 a0 a20 a21 nc a19 w e1 e0 e2 byte a6 a3 a8 a9 a10 a2 a7 v pen a1 a4 a5 a12 a13 a11 a15 a14 rp v ss dq13 dq15 v dd dq5 g v ss v ssq nc nc
m58lw032d 8/51 figure 4. tbga64 connections (top view through package) ai06236b dq6 a1 v ssq v dd dq10 v dd dq7 dq5 v ddq dq2 h dq14 v ss dq13 d a16 a20 e0 a9 c a17 a21 a11 a15 byte a8 b a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a7 a3 a4 a5 g f e dq0 a6 v pen a18 a10 a12 rp dq15 sts dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss du du du du du du du du nc nc e2 nc e1 a0
9/51 m58lw032d figure 5. block addresses note: also see appendix a, table 23 for a full listing of the block addresses ai06238b 1 mbit or 128 kbytes 1fffffh 1f0000h 1 mbit or 128 kbytes 01ffffh 010000h 1 mbit or 128 kbytes 00ffffh 000000h byte (x8) bus width word (x16) bus width 1 mbit or 128 kbytes 1effffh 1e0000h total of 32 1 mbit blocks 3fffffh 3e0000h 03ffffh 020000h 01ffffh 000000h 3dffffh 3c0000h 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords
m58lw032d 10/51 signal descriptions see figure 2, logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address input (a0). the a0 address input is used to select the higher or lower byte in x8 mode. it is not used in x16 mode (where a1 is the lowest significant bit). address inputs (a1-a21). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the program/erase con- troller. the device must be enabled (refer to table 2, de- vice enable) when selecting the addresses. the address inputs are latched on the rising edge of write enable or on the first edge of chip enables e0, e1 or e2 that disable the device, whichever occurs first. data inputs/outputs (dq0-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the program/erase controller. when used to input data or write commands they are latched on the rising edge of write enable or the first edge of chip enables e0, e1 or e2 that disable the device, whichever occurs first. when the device is enabled and output enable is low, v il (refer to table 2, device enable), the data bus outputs data from the memory array, the elec- tronic signature, the block protection status, the cfi information or the contents of the status reg- ister. the data bus is high impedance when the device is deselected, output enable is high, v ih, or the reset/power-down signal is low, v il . when the program/erase controller is active the ready/ busy status is given on dq7. chip enables (e0, e1, e2). the chip enable in- puts e0, e1 and e2 activate the memory control logic, input buffers, decoders and sense amplifi- ers. the device is selected at the first edge of chip enables e0, e1 or e2 that enable the device and deselected at the first edge of chip enables e0, e1 or e2 that disable the device. refer to table 2, device enable for more details. when the chip enable inputs deselect the memo- ry, power consumption is reduced to the standby level, i dd1 . output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation. when output enable, g , is at v ih the outputs are high impedance. write enable (w ). the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able. reset/power-down (rp ). the reset/power- down pin can be used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset/ power-down low, v il , for at least t plph . when reset/power-down is low, v il , the status regis- ter information is cleared and the power consump- tion is reduced to power-down level. the device is deselected and outputs are high impedance. if re- set/power-down goes low, v il ,during a block erase, a write to buffer and program or a block protect/unprotect the operation is aborted and the data may be corrupted. in this case the sts pin stays low, v il , for a maximum timing of t plph + t ph- bh, until the completion of the reset/power-down pulse. after reset/power-down goes high, v ih , the memory will be ready for bus read and bus write operations after t phqv . note that sts does not fall during a reset, see ready/busy output section. in an application, it is recommended to associate reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset opera- tion occurs while the memory is performing an erase or program operation, the memory may out- put the status register information instead of be- ing initialized to the default asynchronous random read. byte/word organization select (byte ). the byte/word organization select pin is used to switch between the x8 and x16 bus widths of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode. status/(ready/busy) (sts). the sts signal is an open drain output that can be used to identify the program/erase controller status. it can be configured in two modes: n ready/busy - the pin is low, v ol , during program and erase operations and high impedance when the memory is ready for any read, program or erase operation. n status - the pin gives a pulsing signal to indicate the end of a program or block erase operation. after power-up or reset the sts pin is configured in ready/busy mode. the pin can be configured for status mode using the configure sts com- mand. when the program/erase controller is idle, or sus- pended, sts can float high through a pull-up re-
11/51 m58lw032d sistor. the use of an open-drain output allows the sts pins from several memories to be connected to a single pull-up resistor (a low will indicate that one, or more, of the memories is busy). sts is not low during a reset unless the reset was applied when the program/erase controller was active. program/erase enable (v pen ). the program/ erase enable input, v pen, is used to protect all blocks, preventing program and erase operations from affecting their data. program/erase enable must be kept high during all program/erase controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. v dd supply voltage. v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid any condition that would result in data corruption. v ss ground. ground, v ss, is the reference for the core power supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). see fig- ure 8, ac measurement load circuit. table 2. device enable note: for single device operations, e2 and e1 can be connected to v ss . e2 e1 e0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled
m58lw032d 12/51 bus operations there are five standard bus operations that control the memory. each of these is described in this section, see tables 3, bus operations, for a sum- mary. on power-up or after a hardware reset the mem- ory defaults to read array mode (page read). typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. bus read. bus read operations are used to out- put the contents of the memory array, the elec- tronic signature, the status register, the common flash interface and the block protection status. a valid bus operation involves setting the desired address on the address inputs, enabling the de- vice (refer to table 2, device enable), applying a low signal, v il , to output enable and keeping write enable high, v ih . the data read depends on the previous command written to the memory (see command interface section). see figure 9, bus read ac waveforms, and ta- ble 15, bus read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write com- mands to the memory or latch addresses and input data to be programmed. a valid bus write operation begins by setting the desired address on the address inputs and en- abling the device (refer to chip enable section). the address inputs are latched by the command interface on the rising edge of write enable or the first edge of e0, e1 or e2 that disables the device (refer to table 2, device enable). the data input/outputs are latched by the com- mand interface on the rising edge of write enable or the first edge of e0, e1 or e2 that disables the device whichever occurs first. output enable must remain high, v ih , during the bus write operation. see figures 11, and 12, write ac waveforms, and tables 17 and 18, write and chip enable con- trolled write ac characteristics, for details of the timing requirements. output disable. the data inputs/outputs are high impedance when the output enable is at v ih . power-down. the memory is in power-down mode when reset/power-down, rp , is low. the power consumption is reduced to the power-down level, i dd2 , and the outputs are high impedance, independent of chip enable, output enable or write enable. standby. standby disables most of the internal circuitry, allowing a substantial reduction of the current consumption. the memory is in standby when chip enable is at v ih . the power consump- tion is reduced to the standby level i dd1 and the outputs are set to high impedance, independently of the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. table 3. bus operations note: 1. dq8-dq15 are high z in x8 mode. 2. x = dont care v il or v ih . bus operation e0, e1 or e2 g w rp a1-a21 (x16) a0-a21 (x8) dq0-dq15 (x16) dq0-dq7 (x8) (1) bus read v il v il v ih v ih address data output bus write v il v ih v il v ih address data input output disable v il v ih v ih v ih x high z power-down x x x v il x high z standby v ih xx v ih x high z
13/51 m58lw032d read modes read operations in the m58lw032d are asyn- chronous. the device outputs the data corre- sponding to the address latched, that is the memory array, status register, common flash in- terface, electronic signature or block protection status depending on the command issued. during read operations, if the bus is inactive for a time equivalent to t avqv , the device automatically enters auto low power mode. in this mode the in- ternal supply current is reduced to the auto low power supply current, i dd5 . the data inputs/out- puts will still output data if a bus read operation is in progress. read operations can be performed in two different ways, random read (where each bus read oper- ation accesses a different page) and page read. in page read mode a page of data is internally read and stored in a page buffer. each memory page is a 4 words or 8 bytes and has the same a3-a21. in x8 mode only a0, a1 and a2 may change, in x16 mode only a1 and a2 may change. the first read operation within the page has the normal access time (t avqv ), subsequent reads within the same page have much shorter access times (t avqv1 ). if the page changes then the nor- mal, longer timings apply again. see figure 10, page read ac waveforms and table 16, page read ac characteristics for de- tails on when the outputs become valid.
m58lw032d 14/51 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. the commands are summarized in table 4, commands. refer to table 4 in conjunction with the text descriptions below. after power-up or a reset operation the memory enters read mode. read memory array command. the read mem- ory array command is used to return the memory to read mode. one bus write cycle is required to issue the read memory array command and re- turn the memory to read mode. once the com- mand is issued the memory remains in read mode until another command is issued. from read mode bus read operations will access the memory array. after power-up or a reset the mem- ory defaults to read array mode (page read). while the program/erase controller is executing a program, erase, block protect, blocks unprotect or protection register program operation the memory will not accept the read memory array command until the operation completes. read electronic signature command. the read electronic signature command is used to read the manufacturer code, the device code, the block protection status and the protection register. one bus write cycle is required to issue the read electronic signature command. once the com- mand is issued subsequent bus read operations read the manufacturer code, the device code, the block protection status or the protection register until another command is issued. refer to table 6, read electronic signature, tables 7 and 8, word and byte-wide read protection register and fig- ure 6, protection register memory map for infor- mation on the addresses. read query command. the read query com- mand is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations read from the common flash in- terface memory area. see appendix b, tables 24, 25, 26, 27, 28 and 29 for details on the information contained in the common flash interface (cfi) memory area. read status register command. the read sta- tus register command is used to read the status register. one bus write cycle is required to issue the read status register command. once the command is issued subsequent bus read opera- tions read the status register until another com- mand is issued. the status register information is present on the output data bus (dq1-dq7) when the device is en- abled and output enable is low, v il . see the section on the status register and table 10 for details on the definitions of the status reg- ister bits clear status register command. the clear sta- tus register command can be used to reset bits sr1, sr3, sr4 and sr5 in the status register to 0. one bus write is required to issue the clear status register command. the bits in the status register are sticky and do not automatically return to 0 when a new write to buffer and program, erase, block protect, block unprotect or protection register program com- mand is issued. if any error occurs then it is essen- tial to clear any error bits in the status register by issuing the clear status register command before attempting a new program, erase or resume command. block erase command. the block erase com- mand can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the second bus write cycle latches the block address and starts the program/erase con- troller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operation the memory will only accept the read status register command and the program/erase suspend command. all other commands will be ignored. typical erase times are given in table 9. see appendix c, figure 18, block erase flow- chart and pseudo code, for a suggested flowchart on using the block erase command. word/byte program command. the word/ byte program command is used to program a sin- gle word or byte in the memory array. two bus write operations are required to issue the com- mand; the first write cycle sets up the word pro- gram command, the second write cycle latches the address and data to be programmed, and starts the program/erase controller. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command or by using the
15/51 m58lw032d blocks temporary unprotect feature of the reset/ power-down pin, rp . write to buffer and program command. the write to buffer and program command is used to program the memory array. up to 16 words/32 bytes can be loaded into the write buffer and programmed into the memory. each write buffer has the same a5-a21 address- es. in byte-wide mode only a0-a4 may change in word-wide mode only a1-a4 may change, in . four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. is- sue the set up command with the selected memory block address where the program op- eration should occur (any address in the block where the values will be programmed can be used). any bus read operations will start to out- put the status register after the 1st cycle. 2. use one bus write operation to write the same block address along with the value n on the data inputs/output, where n+1 is the number of words/bytes to be programmed. 3. use n+1 bus write operations to load the ad- dress and data for each word into the write buffer. see the constraints on the address com- binations listed below. the addresses must have the same a5-a21. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the oper- ation without affecting the data in the memory ar- ray. the status register should be cleared before re-issuing the command. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. see appendix c, figure 16, write to buffer and program flowchart and pseudo code, for a sug- gested flowchart on using the write to buffer and program command. program/erase suspend command. the pro- gram/erase suspend comm and is used to pause a word/byte program, write to buffer and program or erase operation. the command will only be ac- cepted during a program or an erase operation. it can be issued at any time during an erase opera- tion but will only be accepted during a word pro- gram or write to buffer and program command if the program/erase controller is running. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (sr7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/ erase controller has paused. after the program/ erase controller has paused, the memory will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing it is possible for the op- eration to complete. once the program/erase controller status bit (sr7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (sr2) or the erase suspend status bit (sr6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 9. during program/erase suspend the read memo- ry array, read status register, read electronic signature, read query and program/erase re- sume commands will be accepted by the com- mand interface. additionally, if the suspended operation was erase then the write to buffer and program, and the program suspend commands will also be accepted. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase re- sume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed correctly. see appendix c, figure 17, program suspend & resume flowchart and pseudo code, and figure 19, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command. the pro- gram/erase resume command can be used to re- start the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. once the com- mand is issued subsequent bus read operations read the status register. block protect command. the block protect command is used to protect a block and prevent program or erase operations from changing the data in it. two bus write cycles are required to is- sue the block protect command; the second bus write cycle latches the block address and starts the program/erase controller. once the command is issued subsequent bus read operations read
m58lw032d 16/51 the status register. see the section on the status register for details on the definitions of the status register bits. during the block protect operation the memory will only accept the read status register command. all other commands will be ignored. typical block protection times are given in table 9. the block protection bits are non-volatile, once set they remain set through reset and power- down/power-up. they are cleared by a blocks un- protect command. see appendix c, figure 20, block protect flow- chart and pseudo code, for a suggested flowchart on using the block protect command. blocks unprotect command. the blocks un- protect command is used to unprotect all of the blocks. two bus write cycles are required to issue the blocks unprotect command; the second bus write cycle starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the block unprotect operation the memory will only accept the read status register com- mand. all other commands will be ignored. typical block protection times are given in table 9. see appendix c, figure 21, block unprotect flow- chart and pseudo code, for a suggested flowchart on using the block unprotect command. protection register program command. the protection register program command is used to program the 64 bit user segment of the protection register. two write cycles are required to issue the protection register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the user-programmable segment can be locked by programming bit 1 of the protection register lock location to 0 (see table 7 and x for word- wide and byte-wide protection addressing). bit 0 of the protection register lock location locks the factory programmed segment and is programmed to 0 in the factory. the locking of the protection register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the protection register, see figure 6, protection register memory map. at- tempting to program a previously protected pro- tection register will result in a status register error. the protection register program cannot be sus- pended. see appendix c, figure 22, protection register program flowchart and pseudo code, for the flowchart for using the protection register program command. configure sts command. the configure sts command is used to configure the status/(ready/busy) pin. after power-up or re- set the sts pin is configured in ready/busy mode. the pin can be configured in status mode using the configure sts command (refer to sta- tus/(ready/busy) section for more details. two write cycles are required to issue the config- ure sts command. n the first bus cycle sets up the configure sts command. n the second specifies one of the four possible configurations (refer to table 5, configuration codes): C ready/busy mode C pulse on erase complete mode C pulse on program complete mode C pulse on erase or program complete mode the device will not accept the configure sts com- mand while the program/erase controller is busy or during program/erase suspend. when sts pin is pulsing it remains low for a typical time of 250ns. any invalid configuration code will set an error in the status register.
17/51 m58lw032d table 4. commands note: 1. x dont care; ra read address, rd read data, ida identifier address, idd identifier data, srd status register data, pa p rogram address; pd program data, qa query address, qd query data, ba any address in the block, pra protection register address, prd protection register data, cc configuration code. 2. for identifier addresses and data refer to table 6, read electronic signature. 3. for query address and data refer to appendix b, cfi. table 5. configuration codes note: 1. dq2-dq7 are reserved 2. when sts pin is pulsing it remains low for a typical time of 250ns. command cycles bus operations 1st cycle 2nd cycle subsequent final op. addr. data op. addr. data op. addr. data op. addr. data read memory array 3 2 write x ffh read ra rd read electronic signature 3 2 write x 90h read ida (2) idd (2) read status register 2 write x 70h read x srd read query 3 2 write x 98h read qa (3) qd (3) clear status register 1 write x 50h block erase 2 write x 20h write ba d0 word/byte program 2 write x 40h 10h write pa pd write to buffer and program 4 + n write ba e8h write ba n write pa pd write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h block protect 2 write x 60h write ba 01h blocks unprotect 2 write x 60h write x d0h protection register program 2 write x c0h write pra prd configure sts command 2 write x b8h write x cc configuration code dq1 dq2 mode sts pin description 00h 0 0 ready/busy v ol during p/e operations hi-z when the memory is ready the sts pin is low during program and erase operations and high impedance when the memory is ready for any read, program or erase operation. 01h 0 1 pulse on erase complete pulse low then high when operation completed (2) supplies a system interrupt pulse at the end of a block erase operation. 02h 1 0 pulse on program complete supplies a system interrupt pulse at the end of a program operation. 03h 1 1 pulse on erase or program complete supplies a system interrupt pulse at the end of a block erase or program operation.
m58lw032d 18/51 table 6. read electronic signature note: 1. sba is the start base address of each block, prd is protection register data. 2. base address, refer to figure 6 and tables 7 and 8 for more information. 3. a0 is not used in read electronic signature in either x8 or x16 mode. the data is always presented on the lower byte in x16 m ode. figure 6. protection register memory map table 7. word-wide read protection register code bus width address (a21-a1) (3) data (dq15-dq0) manufacturer code x8 000000h 20h x16 0020h device code x8 000001h 16h x16 0016h block protection status x8 sba (1) +02h 00h (block unprotected) 01h (block protected) x16 0000h (block unprotected) 0001h (block protected) protection register x8, x16 000080h (2) prd (1) word use a8 a7 a6 a5 a4 a3 a2 a1 lock factory, user 10000000 0 factory (unique id) 10000001 1 factory (unique id) 10000010 2 factory (unique id) 10000011 3 factory (unique id) 10000100 4 user 10000101 5 user 10000110 6 user 10000111 7 user 10001000 ai05501 user programmable unique device number protection register lock 1 0 88h 85h 84h 81h 80h word address
19/51 m58lw032d table 8. byte-wide read protection register word use a8 a7 a6 a5 a4 a3 a2 a1 lock factory, user 10000000 lock factory, user 10000000 0 factory (unique id) 10000001 1 factory (unique id) 10000001 2 factory (unique id) 10000010 3 factory (unique id) 10000010 4 factory (unique id) 10000011 5 factory (unique id) 10000011 6 factory (unique id) 10000100 7 factory (unique id) 10000100 8 user 10000101 9 user 10000101 a user 10000110 b user 10000110 c user 10000111 d user 10000111 e user 10001000 f user 10001000
m58lw032d 20/51 table 9. program, erase times and program erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. effective byte programming time 6s, effective word programming time 12s. 4. maximum value measured at worst case conditions for both temperature and v dd after 100,000 program/erase cycles. 5. maximum value measured at worst case conditions for both temperature and v dd . parameters m58lw032d unit min typ (1,2) max (2) block (1mb) erase 1.2 4.8 (4) s chip program (write to buffer) 24 72 (4) s chip erase time 37 110 (4) s program write buffer 192 (3) 576 (4) s word/byte program time (word/byte program command) 16 48 (4) s program suspend latency time 1 20 (5) s erase suspend latency time 1 25 (5) s block protect time 18 30 (5) s blocks unprotect time 0.75 1.2 (5) s program/erase cycles (per block) 100,000 cycles data retention 20 years
21/51 m58lw032d status register the status register provides information on the current or previous program, erase, block protect or blocks unprotect operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, blocks unprotect and program/erase re- sume commands. the status register can be read from any address. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable pin or by dis-activating and then reactivating the device (refer to table 2, device enable). status register bits sr5, sr4, sr3 and sr1 are associated with various error conditions and can only be reset with the clear status register com- mand. the status register bits are summarized in table 10, status register bits. refer to table 10 in conjunction with the following text descriptions. program/erase controller status (sr7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low, v ol , the program/erase controller is active and all other status register bits are high imped- ance; when the bit is high, v oh , the program/ erase controller is inactive. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, block protect and blocks unprotect operations the program/erase control- ler status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase con- troller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status and block protection status bits should be tested for errors. erase suspend status (sr6). the erase sus- pend status bit indicates that an erase operation has been suspended and is waiting to be re- sumed. the erase suspend status should only be considered valid when the program/erase con- troller status bit is high (program/erase controller inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is low, v ol , the program/erase controller is active or has com- pleted its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (sr5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). when the erase status bit is low, v ol , the mem- ory has successfully verified that the block has erased correctly or all blocks have been unprotect- ed successfully. when the erase status bit is high, v oh , the erase operation has failed. de- pending on the cause of the failure other status register bits may also be set to high, v oh . n if only the erase status bit (sr5) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. n if the failure is due to an erase or blocks unprotect with v pen low, v ol , then v pen status bit (sr3) is also set high, v oh . n if the failure is due to an erase on a protected block then block protection status bit (sr1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then program status bit (sr4) is also set high, v oh . once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (sr4). the program status bit is used to identify a program or block protect fail- ure. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is low, v ol , the memory has successfully verified that the write buffer has programmed correctly or the block is protected. when the program status bit is high, v oh , the program or block protect operation has failed. depending on the cause of the failure other status register bits may also be set to high, v oh . n if only the program status bit (sr4) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the
m58lw032d 22/51 byte and still failed to verify that the write buffer has programmed correctly or that the block is protected. n if the failure is due to a program or block protect with v pen low, v ol , then v pen status bit (sr3) is also set high, v oh . n if the failure is due to a program on a protected block then block protection status bit (sr1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then erase status bit (sr5) is also set high, v oh . once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pen status (sr3). the v pen status bit can be used to identify if a program, erase, block protec- tion or block unprotection operation has been at- tempted when v pen is low, v il . when the v pen status bit is low, v ol , no pro- gram, erase, block protection or block unprotec- tion operations have been attempted with v pen low, v il , since the last clear status register com- mand, or hardware reset. when the v pen status bit is high, v oh , a program, erase, block protec- tion or block unprotection operation has been at- tempted with v pen low, v il . once set high, the v pen status bit can only be re- set by a clear status register command or a hard- ware reset. if set high it should be reset before a new program, erase, block protection or block unprotection command is issued, otherwise the new command will appear to fail. program suspend status (sr2). the program suspend status bit indicates that a program oper- ation has been suspended and is waiting to be re- sumed. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase con- troller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is low, v ol , the program/erase controller is active or has completed its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (sr1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a protected block. when the block protection status bit is low, v ol , no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is high, v oh , a program (program status bit sr4 set high) or erase (erase status bit sr5 set high) operation has been attempted on a protected block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. reserved (sr0). bit sr0 of the status register is reserved. its value should be masked.
23/51 m58lw032d table 10. status register bits operation sr7 sr6 sr5 sr4 sr3 sr2 sr1 result (hex) program/erase controller active 0 hi-z n/a write buffer not ready 0 hi-z n/a write buffer ready 1 0 0 0 0 0 0 80h write buffer ready in erase suspend 1 1 0 0 0 0 0 c0h program suspended 1 0 0 0 0 1 0 84h program suspended in erase suspend 1 1 0 0 0 1 0 c4h program/block protect completed successfully 100000080h program completed successfully in erase suspend 1100000c0h program/block protect failure due to incorrect command sequence 1011000b0h program failure due to incorrect command sequence in erase suspend 1111000f0h program/block protect failure due to v pen error 100110098h program failure due to v pen error in erase suspend 1101100d8h program failure due to block protection 1 0 0 1 0 0 1 92h program failure due to block protection in erase suspend 1101001d2h program/block protect failure due to cell failure 100100090h program failure due to cell failure in erase suspend 1101000d0h erase suspended 1 1 0 0 0 0 0 c0h erase/blocks unprotect completed successfully 100000080h erase/blocks unprotect failure due to incorrect command sequence 1011000b0h erase/blocks unprotect failure due to v pen error 1010100a8h erase failure due to block protection 1 0 1 0 0 0 1 a2h erase/blocks unprotect failure due to failed cells in block 1010000a0h configure sts error due to invalid configuration code 1011000b0h
m58lw032d 24/51 maximum rating stressing the device above the ratings listed in ta- ble 11, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 11. absolute maximum ratings note: 1. maximum one output short-circuited at a time and for no longer than 1 second. symbol parameter value unit min max t bias temperature under bias C40 125 c t stg storage temperature C55 150 c v io input or output voltage C0.6 v ddq +0.6 v v dd , v ddq supply voltage C0.6 5.0 v i osc output short-circuit current 100 (1) ma
25/51 m58lw032d dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 12, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 12. operating and ac measurement conditions figure 7. ac measurement input output waveform figure 8. ac measurement load circuit table 13. capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter m58lw032d units min max supply voltage (v dd ) 2.7 3.6 v input/output supply voltage (v ddq ) 2.7 3.6 v ambient temperature (t a ) grade 1 0 70 c grade 6 C40 85 c load capacitance (c l ) 30 pf input pulses voltages 0 to v ddq v input and output timing ref. voltages 0.5 v ddq v ai00610 v ddq 0v 0.5 v ddq ai03459 1.3v dq s c l c l includes jig capacitance 3.3k w 1n914 device under test 0.1f v dd v ddq 0.1f symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
m58lw032d 26/51 table 14. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd supply current (random read) e = v il , f=5mhz 20 ma i ddo supply current (page read) e = v il , f=33mhz 29 ma i dd1 supply current (standby) e = v ih , rp = v ih 40 m a i dd5 supply current (auto low-power) e = v il , rp = v ih 40 m a i dd2 supply current (reset/power-down) rp = v il 40 a i dd3 supply current (program or erase, block protect, block unprotect) program or erase operation in progress 30 ma i dd4 supply current (erase/program suspend) e = v ih 40 a v il input low voltage C0.5 0.8 v v ih input high voltage 2 v ddq + 0.5 v v ol output low voltage i ol = 100a 0.2 v v oh output high voltage i oh = C100a v ddq C0.2 v v lko v dd supply voltage (erase and program lockout) 2v v penh v pen supply voltage (block erase, program and block protect) 2.7 3.6 v
27/51 m58lw032d figure 9. bus read ac waveforms note: 1. v ih = device disabled (first edge of e0, e1 or e2), v il = device enabled (first edge of e0, e1 or e2). refer to table 2 for more details. 2. byte can be low or high. table 15. bus read ac characteristics. symbol parameter test condition m58lw032d unit 90 110 t avav address valid to address valid e = v il , g = v il min 90 110 ns t av qv address valid to output valid e = v il , g = v il max 90 110 ns t axqx address transition to output transition e = v il , g = v il min 0 0 ns t blqv byte low (or high) to output valid e = v il , g = v il max 1 1 s t blqz byte low (or high) to output hi-z e = v il , g = v il max 1 1 s t ehqx chip enable high to output transition g = v il min 0 0 ns t ehqz chip enable high to output hi-z g = v il max 25 25 ns t elbl chip enable low to byte low (or high) g = v il max 10 10 ns t elqx chip enable low to output transition g = v il min 0 0 ns t elqv chip enable low to output valid g = v il max 90 110 ns t ghqx output enable high to output transition e = v il min 0 0 ns t ghqz output enable high to output hi-z e = v il max 15 15 ns t glqx output enable low to output transition e = v il min 0 0 ns t glqv output enable low to output valid e = v il max 25 25 ns ai06239b e2, e1, e0 (1) g a0-a21 dq0-dq15 valid taxqx telqx tavqv tglqv tehqz tghqx output tavav tehqx tghqz tglqx telqv byte (2) telbl tblqv tblqz
m58lw032d 28/51 figure 10. page read ac waveforms note: 1. v ih = device disabled (first edge of e0, e1 or e2), v il = device enabled (first edge of e0, e1 or e2). refer to table 2 for more details. table 16. page read ac characteristics note: for other timings see table 15, bus read ac characteristics. symbol parameter test condition m58lw032d unit 90 - 110 t axqx1 address transition to output transition e = v il , g = v il min 6 ns t avqv1 address valid to output valid e = v il , g = v il max 25 ns ai06240 e2, e1, e0 (1) g a3-a21 dq0-dq15 valid taxqx telqx tavqv tglqv tehqx tghqz output output a1-a2 taxqx1 valid valid tghqx tehqz telqv tglqx tavqv1
29/51 m58lw032d figure 11. write ac waveform, write enable controlled note: 1. v ih = device disabled (first edge of e0, e1 or e2), v il = device enabled (first edge of e0, e1 or e2). refer to table 2 for more details. table 17. write ac characteristics, write enable controlled symbol parameter test condition m58lw032d unit 90 - 110 t av wh address valid to write enable high e = v il min 50 ns t dvwh data input valid to write enable high e = v il min 50 ns t elwl chip enable low to write enable low min 0 ns t vphwh program/erase enable high to write enable high min 0 ns t whax write enable high to address transition e = v il min 0 ns t whbl write enable high to status/(ready/busy) low max 500 ns t whdx write enable high to input transition e = v il min 0 ns t wheh write enable high to chip enable high min 0 ns t ghwl output enable high to write enable low min 20 ns t whgl write enable high to output enable low min 35 ns t whwl write enable high to write enable low min 30 ns t wlwh write enable low to write enable high e = v il min 70 ns ai06241 dq0-dq15 sts (ready/busy mode) w a0-a21 e2, e1, e0 (1) g input valid twheh tavwh twlwh telwl v pen twhax twhwl twhdx tdvwh tvphwh twhgl tghwl twhbl
m58lw032d 30/51 figure 12. write ac waveforms, chip enable controlled note: 1. v ih = device disabled (first edge of e0, e1 or e2), v il = device enabled (first edge of e0, e1 or e2). refer to table 2 for more details. table 18. write ac characteristics, chip enable controlled. symbol parameter test condition m58lw032d unit 90 - 110 t av eh address valid to chip enable high w = v il min 50 ns t dveh data input valid to chip enable high w = v il min 50 ns t wlel write enable low to chip enable low min 0 ns t vpheh program/erase enable high to chip enable high min 0 ns t ehax chip enable high to address transition w = v il min 0 ns t ehbl chip enable high to status/(ready/busy) low max 500 ns t ehdx chip enable high to input transition w = v il min 0 ns t ehwh chip enable high to write enable high min 0 ns t ghel output enable high to chip enable low min 20 ns t ehgl chip enable high to output enable low min 35 ns t ehel chip enable high to chip enable low min 30 ns t eleh chip enable low to chip enable high w = v il min 70 ns ai06242 dq0-dq15 sts e2, e1, e0 (1) a0-a21 w g input valid tehwh taveh teleh twlel v pen tehax tehel tehdx tdveh tvpheh tehgl tghel tehbl (ready/busy mode)
31/51 m58lw032d figure 13. reset, power-down and power-up ac waveform note: 1. v ih = device disabled (first edge of e0, e1 or e2), v il = device enabled (first edge of e0, e1 or e2). refer to table 2 for more details. table 19. reset, power-down and power-up ac characteristics symbol parameter m58lw032d unit 90 110 t phqv reset/power-down high to data valid max 130 150 ns t phwl reset/power-down high to write enable low max 1 1 s t plph reset/power-down low to reset/power-down high min 100 100 ns t plbh reset/power-down low to status/(ready/busy) high max 30 30 s t vdhph supply voltages high to reset/power-down high min 0 0 s ai06217b sts w rp e2, e1, e0 (1) , g v dd , v ddq tvdhph tplph tplbh power-up and reset reset during program or erase dq0-dq15 tphqv (ready/busy mode) tphwl
m58lw032d 32/51 package mechanical figure 14. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline note: drawing is not to scale. table 20. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 13.90 14.10 0.5472 0.5551 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n56 56 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
33/51 m58lw032d figure 15. tbga64 - 10x13mm, 8 x 8 ball array 1mm pitch, package outline note: drawing is not to scale. table 21. tbga64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.850 0.0335 b 0.400 0.500 0.0157 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 C C 0.2756 C C ddd 0.100 0.0039 e 1.000 C C 0.0394 C C e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 C C 0.2756 C C fd 1.500 C C 0.0591 C C fe 3.000 C C 0.1181 C C sd 0.500 C C 0.0197 C C se 0.500 C C 0.0197 C C e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
m58lw032d 34/51 part numbering table 22. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m58lw032d 110 n 1 t device type m58 architecture l = page mode operating voltage w = v dd = v ddq = 2.7v to 3.6v device function 032d = 32 mbit (x8, x16), uniform block speed 110 = 110ns 90 = 90ns package n = tsop56: 14 x 20 mm za = tbga64: 10 x 13 mm, 1mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option blank = standard packing t = tape & reel packing e = lead-free package, standard packing f = lead-free package, tape & reel packing
35/51 m58lw032d appendix a. block address table table 23. block addresses block number address range (x8 bus width) address range (x16 bus width) 32 3e0000h-3fffffh 1f0000h-1fffffh 31 3c0000h-3dffffh 1e0000h-1effffh 30 3a0000h-3bffffh 1d0000h-1dffffh 29 380000h-39ffffh 1c0000h-1cffffh 28 360000h-37ffffh 1b0000h-1bffffh 27 340000h-35ffffh 1a0000h-1affffh 26 320000h-33ffffh 190000h-19ffffh 25 300000h-31ffffh 180000h-18ffffh 24 2e0000h-2fffffh 170000h-17ffffh 23 2c0000h-2dffffh 160000h-16ffffh 22 2a0000h-2bffffh 150000h-15ffffh 21 280000h-29ffffh 140000h-14ffffh 20 260000h-27ffffh 130000h-13ffffh 19 240000h-25ffffh 120000h-12ffffh 18 220000h-23ffffh 110000h-11ffffh 17 200000h-21ffffh 100000h-10ffffh 16 1e0000h-1fffffh 0f0000h-0fffffh 15 1c0000h-1dffffh 0e0000h-0effffh 14 1a0000h-1bffffh 0d0000h-0dffffh 13 180000h-19ffffh 0c0000h-0cffffh 12 160000h-17ffffh 0b0000h-0bffffh 11 140000h-15ffffh 0a0000h-0affffh 10 120000h-13ffffh 090000h-09ffffh 9 100000h-11ffffh 080000h-08ffffh 8 0e0000h-0fffffh 070000h-07ffffh 7 0c0000h-0dffffh 060000h-06ffffh 6 0a0000h-0bffffh 050000h-05ffffh 5 080000h-09ffffh 040000h-04ffffh 4 060000h-07ffffh 030000h-03ffffh 3 040000h-05ffffh 020000h-02ffffh 2 020000h-03ffffh 010000h-01ffffh 1 000000h-01ffffh 000000h-00ffffh
m58lw032d 36/51 appendix b. common flash interface - cfi the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 24, 25, 26, 27, 28 and 29 show the addresses used to re- trieve the data. table 24. query structure overview note: 1. offset 15h defines p which points to the primary algorithm extended query address table. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. sba is the start base address for each block. 4. in x8 mode, a0 must be set to v il , otherwise 00h will be output. table 25. cfi - query address and data output note: 1. query data are always presented on dq7-dq0. dq15-dq8 are set to '0'. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. in x8 mode, a0 must be set to v il , otherwise 00h will be output. address sub-section name description x16 x8 (4) 0000h 00h manufacturer code 0001h 02h device code 0010h 20h cfi query identification string command set id and algorithm data offset 001bh 36h system interface information device timing and voltage information 0027h 4eh device geometry definition flash memory layout p(h) (1) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) (sba+02)h block status register block-related information address data description x16 x8 (3) 0010h 20h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 0011h 22h 52h "r" 0012h 24h 59h "y" 0013h 26h 01h primary vendor: command set and control interface id code 0014h 28h 00h 0015h 2ah 31h primary algorithm extended query address table: p(h) 0016h 2ch 00h 0017h 2eh 00h alternate vendor: command set and control interface id code 0018h 30h 00h 0019h 32h 00h alternate algorithm extended query address table 001ah (2) 34h 00h
37/51 m58lw032d table 26. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volts and bit3 to bit0 in mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volts while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. 4. in x8 mode, a0 must be set to v il , otherwise 00h will be output. table 27. device geometry definition note: 1. in x8 mode, a0 must be set to v il , otherwise 00h will be output. address data description x16 x8 (4) 001bh 36h 27h (1) v dd min, 2.7v 001ch 38h 36h (1) v dd max, 3.6v 001dh 3ah 00h (2) v pp min C not available 001eh 3ch 00h (2) v pp max C not available 001fh 3eh 04h 2 n s typical time-out for word, dword prog C not available 0020h 40h 08h 2 n s, typical time-out for max buffer write 0021h 42h 0ah 2 n ms, typical time-out for erase block 0022h 44h 00h (3) 2 n ms, typical time-out for chip erase C not available 0023h 46h 04h 2 n x typical for word dword time-out max C not available 0024h 48h 04h 2 n x typical for buffer write time-out max 0025h 4ah 04h 2 n x typical for individual block erase time-out maximum 0026h 4ch 00h (3) 2 n x typical for chip erase max time-out C not available address data description x16 x8 (1) 0027h 4eh 16h n where 2 n is number of bytes memory size 0028h 50h 02h device interface 0029h 52h 00h organization sync./async. 002ah 54h 05h maximum number of bytes in write buffer, 2 n 002bh 56h 00h 002ch 58h 01h bit7-0 = number of erase block regions in device 002dh 5ah 1fh number (n-1) of erase blocks of identical size; n=64 002eh 5ch 00h 002fh 5eh 00h erase block region information x 256 bytes per erase block (128k bytes) 0030h 60h 02h
m58lw032d 38/51 table 28. block status register note: 1. ba specifies the block address location, a21-a17. 2. in x8 mode, a0 must be set to v il , otherwise 00h will be output. 3. not supported. address data selected block information (ba+2)h (1,2) bit0 0 block unprotected 1 block protected bit1 0 last erase operation ended successfully (3) 1 last erase operation not ended successfully (3) bit7-2 0 reserved for future features
39/51 m58lw032d table 29. extended query information note: 1. bit7 to bit4 are coded in hexadecimal and scaled in volt while bit3 to bit0 are in binary code decimal and scaled in mv. 2. in x8 mode, a0 must be set to v il , otherwise 00h will be output. address data (hex) description offset x16 x8 (2) (p)h 0031h 62h 50h "p" query ascii string - extended table (p+1)h 0032h 64h 52h "r" (p+2)h 0033h 66h 49h "y" (p+3)h 0034h 68h 31h major version number (p+4)h 0035h 6ah 31h minor version number (p+5)h 0036h 6ch ceh optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, protect/unprotect supported (1=yes) bit4, queue erase supported (0=no) bit5, instant individual block locking (0=no) bit6, protection bits supported (1=yes) bit7, page read supported (1=yes) bit8, synchronous read supported (0 =no) bits 9 to 31 reserved for future use (p+6)h 0037h 6eh 00h (p+7)h 0038h 70h 00h (p+8)h 0039h 72h 00h (p+9)h 003ah 74h 01h function allowed after suspend: program allowed after erase suspend (1=yes) bits 7-1 reserved for future use (p+a)h 003bh 76h 01h block status register bit0, block protect bit status active (1=yes) bit1, block lock-down bit status active (not supported) bits 2 to 15 reserved for future use (p+b)h 003ch 78h 00h (p+c)h 003dh 7ah 33h v dd optimum program/erase voltage conditions (p+d)h 003eh 7ch 00h v pp optimum program/erase voltage conditions (p+e)h 003fh 7eh 01h otp protection: no. of protection register fields (p+f)h 0040h 80h 80h protection registers start address, least significant bits (p+10)h 0041h 82h 00h protection registers start address, most significant bits (p+11)h 0042h 84h 03h n where 2 n is number of factory reprogrammed bytes (p+12)h 0043h 86h 03h n where 2 n is number of user programmable bytes (p+13)h 0044h 88h 03h page read: 2 n bytes (n = bits 0-7) (p+14)h 0045h 8ah 00h synchronous mode configuration fields (p+15)h 0046h 8ch reserved for future use
m58lw032d 40/51 appendix c. flow charts figure 16. write to buffer and program flowchart and pseudo code write to buffer e8h command, block address ai05511 start read status register no sr7 = 1 write buffer data, start address yes x = n yes no end no write to buffer timeout write n (1) , block address yes x = 0 write next buffer data, next program address (2) x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) try again later note 1: n+1 is number of words to be programmed note 2: next program address must have same a5-a21. note 3: a full status register check must be done to check the program operation's success.
41/51 m58lw032d figure 17. program suspend & resume flowchart and pseudo code write 70h ai00612b read status register yes no sr7 = 1 yes no sr2 = 1 program continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while sr7 = 1 if sr2 = 0, program completed read memory array command: C write ffh C one or more data reads from other blocks write d0h program erase resume command: C write d0h to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
m58lw032d 42/51 figure 18. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clear status register command) before further program or eras e oper- ations. write 20h ai00613c start write d0h to block address read status register yes no sr7 = 1 yes no sr3 = 0 no sr4, sr5 = 0 v pen invalid error (1) command sequence error erase command: C write 20h C write d0h to block address (a12-a17) (memory enters read status register after the erase command) do: C read status register C if program/erase suspend command given execute suspend erase loop while sr7 = 1 if sr3 = 1, v pen invalid error: C error handler if sr4, sr5 = 1, command sequence error: C error handler yes no sr5 = 0 erase error (1) yes no suspend suspend loop if sr5 = 1, erase error: C error handler yes end yes no sr1 = 0 erase to protected block error if sr1 = 1, erase to protected block error: C error handler
43/51 m58lw032d figure 19. erase suspend & resume flowchart and pseudo code write 70h ai00615b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while sr7 = 1 if sr6 = 0, erase completed read memory array command: C write ffh C one or more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: C write d0h to resume the erase operation C if the program operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
m58lw032d 44/51 figure 20. block protect flowchart and pseudo code write 01h block address ai06157b yes no sr7 = 1 start write 60h block address write ffh read status register block protect sucessful sr3 = 1 sr4, sr5 = 1,1 sr4 = 1 v pen invalid error invalid command sequence error block protect error yes yes yes no no no block protect command C write 60h, block adress C write 01h, block adress do: C read status register while sr7 = 1 if sr3 = 1, v pen invalid error read memory array command: C write ffh if sr4 = 1, sr5 = 1 invalid command sequence error if sr4 = 1, block protect error
45/51 m58lw032d figure 21. block unprotect flowchart and pseudo code write d0h ai06158b yes no sr7 = 1 start write 60h write ffh read status register blocks unprotect sucessful sr3 = 1 sr4, sr5 = 1,1 sr5 = 1 v pen invalid error invalid command sequence error blocks unprotect error yes yes yes no no no blocks unprotect command C write 60h, block adress C write d0h, block adress do: C read status register while sr7 = 1 if sr3 = 1, v pen invalid error read memory array command: C write ffh if sr4 = 1, sr5 = 1 invalid command sequence error if sr5 = 1, blocks unprotect error
m58lw032d 46/51 figure 22. protection register program flowchart and pseudo code note: pr = protection register write pr address, pr data ai06159b yes no sr7 = 1 start write c0h write ffh read status register pr program sucessful sr1, sr4 = 0,1 v pen invalid error protection register program error protection register program error yes yes yes no no no protection register program command C write c0h C write protection register address, protection register data do: C read status register while sr7 = 1 read memory array command: C write ffh if sr1 = 0, sr4 = 1 protection register program error sr3, sr4 = 1,1 if sr3 = 1, sr4 = 1 v pen invalid error sr1, sr4 = 1,1 if sr1 = 1, sr4 = 1 program error due to protection register protection
47/51 m58lw032d figure 23. command interface and program erase controller flowchart (a) ai03618 read signature yes no 90h read status yes 70h no clear status yes 50h no program buffer load yes e8h no erase set-up yes 20h (1) no erase command error yes ffh wait for command write read array yes d0h no a b no c cfi query yes 98h no d0h yes no program command error note 1. the erase command (20h) can only be issued if the flash is not already in erase suspend.
m58lw032d 48/51 figure 24. command interface and program erase controller flowchart (b) read status yes no 70h b erase yes ready ? no a b0h no read status yes ready ? no erase suspend yes d0h read array yes erase suspended read status (read status) yes (erase resume) no read status 90h no read signature yes 98h no cfi query yes e8h no program buffer load yes c ai03619 program/erase controller status bit in the status register read status d0h yes no no program command error wait for command write ffh yes read array no
49/51 m58lw032d figure 25. command interface and program erase controller flowchart (c). read status yes no 70h b program yes ready ? no c b0h no read status yes ready ? no program suspend yes d0h read array yes program suspended read status (read status) yes no (program resume) no read status 90h no read signature yes 98h no cfi query yes ai00618 program/erase controller status bit in the status register read status read array yes no ffh wait for command write
m58lw032d 50/51 revision history table 30. document revision history date version revision details 04-jun-2002 -01 first issue 16-jun-2002 1.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 01 becomes 1.0). figure 5 modified. t whdx and t whax modified in table 17. 06-aug-2002 2.0 device code changed, word effective programming time modified, v ddq range modified (esp. in tables 12 and 22, and v ddq removed from note 1 below table 9). block erase and program write buffer time parameters modified in table 9. 90ns speed class added (table 15, 16, 17, 18, 19 and 22 modified accordingly). figure 2, logic diagram modified. v dd , v ddq , v ss and v ssq pin descriptions modified. document status changed from product preview to preliminary data. 14-oct-2002 2.1 a0 address line described separately from others (a1-a21) in table 1 and in signal descriptions paragraph. address lines modified in table 3, bus operations. byte signal added to figure 9, bus read ac waveforms, timings t elbl , t blqv and t blqz added to table 15, bus read ac characteristics, timings t av lh and t ellh removed from table 18, write ac characteristics, chip enable controlled. chip enable controlled. write 70h removed from flowchart figures 17 and 19. table 3, bus operations, clarified. revision history moved to after the appendices. 16-dec-2002 2.2 table 9, program, erase times and program erase endurance cycles table modified. table 6, read electronic signature table clarified. certain du connections changed to nc in table 4, tbga64 connections (top view through package). x8 address modified in table 24, query structure overview. note regarding a0 value in x8 mode added to all cfi tables. block protect setup command address modified in table 4, commands. data and descriptions clarified in cfi table 29, extended query information. i osc parameter added to absolute maximum ratings table. i dd and v lko clarified and i ddo and v penh parameters added to dc characteristics table. t phwl parameter added to reset, power-down and power-up ac waveforms figure and characteristics table. 30-may-2003 2.3 summary description clarified, bus operations clarified, read modes section added, status register bit nomenclature modified, v pen invalid error clarified in flowcharts. lead-free packing options added to ordering information scheme. 12-sep-2003 2.4 t ehax and t ehdx minimum values modified in table 18, write ac characteristics, chip enable controlled. full datasheet.
51/51 m58lw032d information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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